ARM’s DynamIQ Focuses on Performance, Efficiency, Redundancy, Scalability, and Latency
There has been a lot of progress made in mobile SoCs over the last 10 years. We have come a long way since the single core chips from a decade ago. The biggest advancement in chipsets since those days has likely been ARM’s big.LITTLE cluster design which has helped massively improve both performance and power efficiency at the same time. To continue that trend, this week ARM announced DynamIQ.
ARM’s big.LITTLE cluster design allowed for two to four power efficient cores to be paired with two to four high-performance cores. We even had companies like MediaTek use this design to produce three core clusters for their SoCs with 10 cores packed inside them. ARM wants to take this idea but improve both performance and efficiency while focusing on scalability as well as latency. These last two facets are particularly important for the automotive, artificial intelligence, and machine learning markets.
It is these three markets where ARM sees a lot of growth happening over the next 5 years too. The design of ARM’s DynamIQ is made up of eight cores per cluster, and each of these clusters can have their own unique set of cores. This means the cores in each cluster can be from different ARM Cortex-A families in different configurations. The new design allows for each of these cores to be controlled independently for voltage and frequency, as well as sleep states.
Part of ARM’s focus on scalability is also about providing redundancy, which would allow for what seems to be an unlimited number of clusters to be used. If one of the clusters fail, another one could take its place. This would be important for the automotive industry as it would be dangerous to have a cluster fail at a bad moment. There are still a lot of questions that need to be answered since ARM didn’t go into details about things such as cache hierarchy, the new memory sub-system design, and more.
However, ARM did promise to reveal more details about DynamIQ in the coming months.